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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 59: GTX Transceiver Transmitter Switching Characteristics (Cont’d)
Symbol
TJ 10.3125
DJ 10.3125
TJ 9.953
DJ 9.953
TJ 9.8
DJ 9.8
TJ 8.0
DJ 8.0
TJ 6.6_QPLL
DJ 6.6_QPLL
TJ 6.6_CPLL
DJ 6.6_CPLL
TJ 5.0
DJ 5.0
TJ 4.25
DJ 4.25
TJ 3.75
DJ 3.75
TJ 3.2
DJ 3.2
TJ 3.2L
DJ 3.2L
TJ 2.5
DJ 2.5
TJ 1.25
DJ 1.25
TJ 500
DJ 500
Description
Total Jitter (2)(4)
Deterministic Jitter (2)(4)
Total Jitter (2)(4)
Deterministic Jitter (2)(4)
Total Jitter (2)(4)
Deterministic Jitter (2)(4)
Total Jitter (2)(4)
Deterministic Jitter (2)(4)
Total Jitter (2)(4)
Deterministic Jitter (2)(4)
Total Jitter (3)(4)
Deterministic Jitter (3)(4)
Total Jitter (3)(4)
Deterministic Jitter (3)(4)
Total Jitter (3)(4)
Deterministic Jitter (3)(4)
Total Jitter (3)(4)
Deterministic Jitter (3)(4)
Total Jitter (3)(4)
Deterministic Jitter (3)(4)
Total Jitter (3)(4)
Deterministic Jitter (3)(4)
Total Jitter (3)(4)
Deterministic Jitter (3)(4)
Total Jitter (3)(4)
Deterministic Jitter (3)(4)
Total Jitter (3)(4)
Deterministic Jitter (3)(4)
Condition
10.3125 Gb/s
9.953 Gb/s
9.8 Gb/s
8.0 Gb/s
6.6 Gb/s
6.6 Gb/s
5.0 Gb/s
4.25 Gb/s
3.75 Gb/s
3.20 Gb/s (5)
3.20 Gb/s (6)
2.5 Gb/s (7)
1.25 Gb/s (8)
500 Mb/s
Min
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Typ
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Max
0.28
0.17
0.28
0.17
0.28
0.17
0.30
0.15
0.28
0.17
0.30
0.15
0.30
0.15
0.30
0.15
0.30
0.15
0.2
0.1
0.32
0.16
0.20
0.08
0.15
0.06
0.1
0.03
Units
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
Using same REFCLK input with TX phase alignment enabled for up to 12 consecutive transmitters (three fully populated GTX Quads).
Using QPLL_FBDIV = 40, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations.
Using CPLL_FBDIV = 2, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations.
All jitter values are based on a bit-error ratio of 1e -12 .
CPLL frequency at 3.2 GHz and TXOUT_DIV = 2.
CPLL frequency at 1.6 GHz and TXOUT_DIV = 1.
CPLL frequency at 2.5 GHz and TXOUT_DIV = 2.
CPLL frequency at 2.5 GHz and TXOUT_DIV = 4.
DS182 (v2.8) March 4, 2014
Product Specification
www.xilinx.com
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